A simplistic view of electronic design automation may refer to inputting a Register Transfer Level (RTL) or behavior representation of a circuit into a synthesis tool to create a gate-level netlist representation of a circuit, (i.e., the logic and gates that will perform the desired functions outlined in the RTL). In other words, the synthesis tool takes the behavior requirements and determines what hardware to use. A wire-load model is used by a synthesis tool to estimate wire characteristics (e.g., interconnect delay) in the absence of physical layout data. For a wire with a given fanout, the wire-load model specifies the capacitance and resistance per unit area or length of the wire. The resulting timing of an integrated circuit that is responsive to the RTL and netlist is actually based upon the physical layout that is generated after placement and routing. However during the synthesis of the functional logic in the integrated circuit, a physical layout of the integrated circuit is typically unavailable.
Silicon foundries or cell library vendors may develop wire-load models based on statistical information taken from a variety of example designs. The example designs may test the wire characteristics at a variety of cell areas. That is, the wire-load model is typically an area-based wire-load model that is a function of the area of the design. There are several problems with this method of wire-load model generation.
An area-based wire-load model is based on the area consumed by the design. One problem with an area-based wire-load model supplied by the vendor is that area is typically the only one feature that may affect design timing given a synthesis library. Other physical factors may have an affect on the circuit timing or delay but are not accounted for in an area based wire-load model.
A second problem with the wire-load model generation is the vendor's assumptions and constraints when calculating the wire-load model are unknown and may not be applicable to the user's scenario or application. In other words, the conditions under which the wire-load model was calculated may be unsuitable for or incompatible with the user's circuit design. Users may blindly use the supplied wire-load model without any information as to how the model was obtained. Using a wire-load model without knowledge of how closely it relates to a design may lead to inaccurate delay calculations.
A third problem with the wire-load model generation is that vendors may choose a conservative or overly pessimistic wire-load model. That is, a vendor may choose a conservative capacitance value to represent an area which is greater than the capacitance value of most of the example designs that are in the area. However a conservative capacitance value may not be appropriate.
In addition to the wire-load model generation issues, there may also be problems with the way in which the wire-load model is utilized. A wire-load model may include a plurality of different tables based on the area of a circuit design. Even though, the area of the circuit design may change as the design is optimized. Usage in this manner does not take into account the changes in size or area during optimization. Changes in a circuit design during optimization, without re-evaluating how the wire-load model was used in timing delay calculations, may also result in inaccurate timing delays for the nets in the integrated circuit.
It is desirable to generate a more accurate wire-load model that may be used without some or all of the limitations of conventional techniques.